Certain abbreviations found in the description and/or in the figures are herewith defined as follows:                AN access node        APP a posteriori probability        ASIC application specific integrated circuit        BP belief propagation        DFU decoding function unit        DP data processor        DSPs digital signal processors        FEC forward error correction        FER frame error rate        FPGA field programmable gate array        LBP layered belief propagation        LDPC low density parity check        MEM memory        PCM parity check matrix        PROG program        RF radio frequency        RX receiver        SBP standard belief propagation        SNR signal to noise ratio        TRANS transceiver        TX transmitter        UE user equipment        WiMAX Worldwide Interoperability for Microwave Access        
In typical wireless communication systems hardware resources are limited (e.g., fully parallel architecture is not an acceptable solution because of the large area occupation on a chip, and small or no flexibility), therefore decoding based on LBP is applied. A major advantage of a LBP decoding algorithm in comparison with an SBP decoding algorithm is that the LBP decoding algorithm features a convergence that is approximately two times faster due to the optimized scheduling of reliability messages.
Decoding is performed in layers (e.g., set of independent rows of the PCM) where the APPs are improved from one layer to another. The decoding process in the next layer will start when APPs of the previous layer are updated.
See D. Hocevar, “A reduced complexity decoder architecture via layered decoding of LDPC codes,” in Signal Processing Systems SIPS 2004. IEEE Workshop on, pp. 107-112, October 2004; M. Mansour and N. Shanbhag, “High-throughput LDPC decoders,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 976-996, December 2003; and P. Radosavljevic, A. de Baynast, and J. R. Cavallaro, “Optimized message passing schedules for LDPC decoding.” 39th Asilomar Conference on Signals, Systems and Computers, November 2005.
In S. Chung, T. Richardson, and R. Urbanke, “Analysis of sum-product decoding of low-density parity-check codes using a Gaussian approximation,” IEEE Trans. Inform. Theory, vol. 47, pp. 657-670, February 2001 an optimization of random PCMs was proposed. This optimization is equivalent to optimizing the profile of a random PCM. The profile is defined by two polynomials, ρ(x) and λ(x) which characterize the weight distribution of the columns and rows of the PCM, which is optimized through a density evolution analysis.
On the other hand, Mansour proposed an architecture-aware PCM design in order to achieve an acceptable trade-off between hardware resources and decoding throughput. The PCM is block-structured where each sub-block is a shift identity matrix. Only regular codes were considered and consequently bit/frame error rate performances are relatively poor. For further reference see: A. Prabhakar, K. Narayanan, “Pseudorandom construction of low-density parity-check codes using linear congruential sequences”, IEEE Transactions on Communications, Volume 50, Issue 9, Page(s):1389-1396, September 2002.
In order to support the IEEE 802.11n wireless and WiMAX standards, LDPC decoders should achieve decoding throughput of about 1 Gbit/sec while using limited hardware parallelism (semi-parallel decoder). The decoder architecture needs to be scalable in order to support decoding of wide range of code rates and codeword sizes. Block structured parity check matrices with 24 sub-block columns are proposed in IEEE 802.11n standard and thus decoder architecture should support them.
While a fully parallel architecture with random PCM may achieve a high throughput, it suffers extremely large area occupation since the supported PCMs are not architecture-aware. Block-structured PCMs for semi-parallel architecture have been utilized in order to reduce the decoder area. However, for achieving Gigabits/s throughput, PCMs should be optimized with tighter architecture-aware constraints.